A typical successive approximation converter has one input, a test input, coupled to a signal to be approximated, and the other input receives a successive approximation value generated by a logic circuit commonly referred to as a successive approximation register (SAR). During each clock cycle, a comparator produces an output used by the successive approximation register to produce the next successive approximation value. Consequently, the successive approximation register performs one bit of conversion per clock cycle. For example, for a successive approximation register having N bits, where N is an integer greater than zero, the N bit successive approximation register requires N clock cycles to perform the conversion.
For example, for a comparator that has the test input connected to the negative input and the successive approximation register connected to the positive input with a reference voltage (Vref), during the first clock period compares the test input to the most significant bit (MSB) of the successive approximation value, e.g., the most significant bit of the successive approximation register is raised high. If the output of the comparator remains high, then the input lies somewhere between 0 and Vref/2, and the MSB is reset to 0. However, if the comparator output is low, then the input signal is somewhere between Vref/2 and Vref, and the MSB is set high. During the next clock period, the MSB-1 bit is evaluated in the same manner. This procedure is repeated such that at the end of N clock periods all N bits have been resolved.
The test input can be sampled by using a sample and hold to freeze the voltage. Alternatively, coherent undersampling digitizers (CUD) have been developed that sample a repeating waveform repeatedly at the same point in its period, but each sample occurs during a different cycle. The coherent undersampling digitizers sample at a rate less than the Nyquist rate, which is possible because of the repetitive nature of the test stimuli. Repetitive sampling allows the sampling theorem to be satisfied without directly sampling a signal at greater than twice the highest frequency component of the signal. The CUD architecture is useful for testing new devices, as frequently the new device being tested operates at a speed that is faster than the testing equipment.
The CUD architectures employs a high-speed comparator, strobed by a divided down version of a clock source to make the successive approximation decisions. The stimulus for the device under test (DUT) is produced by a high-speed signal generator, which is driven by a clock source, which can be different than the clock source used for making successive approximation decisions.
Since the comparator strobe slips to the next sampling point on each rising edge, a modified SAR approach is used. Instead of iterating on the same sampling point N times, the conversion is performed in a shuffled order. The first S strobes (where S is an integer greater than zero indicating the number of sampling points on the repetitive test waveform) will determine the most significant bits, e.g. MSB[0] through MSB[S−1]. The next S strobes will determine MSB-1[0] through MSB-1 [S−1], which continues until LSB[0] through LSB[S−1] are determined. Using this algorithm, all of the sample points are computed simultaneously and the CUD uses a S×N memory to store the results. Alternatively, the CUD can determine each sample point individually by ignoring strobes for sample points between the sample point being determined, e.g., determine MSB[0], skip S−1 strobes, determine MSB-1[0], skip S−1 strobes . . . until LSB[0] is determined, and repeat for each sample point.
Implementations of these and other architectures have worked very well for high-speed low-resolution applications, such as for example capturing a sub-nanosecond rising edge of a square wave. However, attempts at medium speed, high-resolution sampling have proven problematic. Some of the difficulties at higher resolution are due to the inherent hysteresis of the comparator circuitry. For example, when the successive approximation register's digital to analog converter's voltage approaches that of the input signal, the comparator must make a decision based on a small voltage difference. Comparator hysteresis can also introduce non-linearity and corrupt the measurement. The effects of hysteresis thus can limit the effective resolution of the SAR or digitizer to an unacceptable level.